1. Field of the Invention
The present invention is related to an electrically programmable semiconductor memory device, and particularly among such semiconductor memory devices, is related to a nonvolatile semiconductor memory device.
2. Description of the Related Art
Demand for a nonvolatile semiconductor memory device that is small and has a large capacity has been increasing rapidly, and a NAND type flash memory, in which higher integration and larger capacity can be expected, has attracted attention. Further micro processing of wiring patterns, for example, is required in order to miniaturize a NAND type flash memory. For realizing further micro processing of wiring patterns and so on, a high level of processing technology is required. Therefore, a reduction of the design rules has become difficult. Thus, in recent years, a large number of inventions on semiconductor memory devices, in which a three-dimensional memory cell is placed, has been suggested to raise the degree of integration of the memory (Japanese Patent Laid-Open No. 2003-078044, U.S. Pat. No. 5,599,724, U.S. Pat. No. 5,707,885, and “Masuoka et al. “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEEE TRANSACTION SON ELECTRON DEVICES, VOL. 50, NO. 4, pp 945-951, Apr. 2003”).
Many of the conventional semiconductor memory devices, in which a three dimensional memory cell is placed, need to perform a Photo Etching Process (hereinafter called “PEP”, which represents a so-called process to perform a patterning using a lithography process with a photo resist and a manufacturing process such as etching,). Here, a Photo Etching Process performed with a smallest line width of the design rule is set as “a critical PEP”, and a Photo Etching Process performed with a line width larger than the smallest line width of the design rule is set as “a rough PEP”. In the conventional semiconductor memory device, in which a three-dimensional memory cell is disposed, it is required that the critical PEP number per one layer of a memory cell part should be equal to or more than 3. Additionally, in a conventional semiconductor memory device, there are many of those, in which memory cells are simply stacked, and thus a cost increase caused by three-dimensional manufacturing is inevitable.
Additionally, in a nonvolatile semiconductor memory device, in which memory cells are stacked in three dimensions, variations of processing size and misalignments may occur. In such a case, especially when the misalignment of contact in a channel region, a contact area is reduced, and resistance is increased. These adversely affect reliability of the device. Additionally, when misalignment of a metal wiring layer occurs, the metal wire and a channel of a transistor may short out. This also adversely affects reliability of the device.